Thermal management in electronics products is one of the most challenging problems. As the electronic industry advances, electronic components are often more densely packed together and operate at higher frequencies which cause many of the electronic components to generate large amounts of heat. Some of the challenges include how to efficiently connect heat dissipating components to a heatsink that is most often located outside the enclosure and separated by large gaps or distances to fill. This problem is more acute in the case of passively cooled embedded, industrial and consumer computing which consist of single board computers (SBC) in the ETX, Mini-ITX, Micro-ATX, Nano-ITX, DIN Rail-mounted, industrial rackmount, COM Express, 3.5″ ESB, PCI SBC, PC/104 & PC/104-Plus and many others. Similar problems also exist in many fanless Edge Computer nodes, home IoT Gateways and Smart Home Assistants such as Google Home, Amazon Echo, and Samsung Smartthings.
For example, many current fanless computers and devices address thermal management of heat dissipating components to the outside environment by providing thermal pathways as feasible using metal sheets and bars that connect to cases of the fanless computers and devices. However, in most instances, these thermal pathways connect circuit boards to the mounting locations of the computer case and do not include critical components such as CPUs.
Others have used large thickness thermal gap pads. Although there are some pads with thicknesses as large as 8 mm, their thermal conductivity is typically limited to 2 W/m-K or less and requires high pressure (above 50 psi) interface. W/m-K stands for Watts per meter-Kelvin or ‘k Value’. The comparison of thermal conductivity can be measured by the ‘k Value’. The ‘k Value’, or Thermal Conductivity, specifies the rate of heat transfer in any homogeneous material. Still others use form-in-place thermal compounds. These too suffer from very low thermal conductivity and are difficult to rework. The thermal compounds are also likely to damage components if the dispensing of the thermal compounds is not carefully managed. Throttling down the workloads of processors to reduce heat generation has been used at the expense of loss productivity. External forced air cooling has been used to actively cool SBC (single board computer) cases.
Current industry practices of filling air gaps, interfacing a heatsink with chip components have been limited to 5 mm as an upper bound using thermal interface materials (TIMs). FIG. 1 illustrates a case 10 for Raspberry Pi3 Model B. There are many examples of electronics hardware where different heights of components result in critical chip components like CPUs, memory modules (DIMMs) and solid storage drives (SDD) not adequately served. In the present example, as illustrated in FIG. 1, the case 10 for the Raspberry Pi3 Model B is separated by a gap 12 of over 24 mm.
Large gaps often leave heat-dissipating chip components and modules located inside the enclosure unserved by externally located heatsinks or forced air cooling. This shortcoming seriously limits the processing capability of end products and do not enable the products to realize their full operating potential.
In addition to interfacing across large gaps, an equally critical problem facing the electronic industry is thermally- and/or electrically-interfacing with heat dissipating components with those of flexible and curved surfaces. Currently, most thermal management materials are rigid and are not suitable to interface with non-flat surfaces. Of the available TIMs (thermal interface materials) that are flexible, thermal conductivity is quite low (below 2 W/m-K) and the pressure necessary to maintain desired contact exceeds 50 psi.
The problem is exasperated as advances in IC packaging methodology continue to evolve. For example, multiple chips arranged in a planar or stacked configuration with an interposer for communication known as 2.5D/3D SiP (System-in-Package) methodology can include multiple integrated circuits (like CPU SoC, ASIC, memory, analog, and passive components) inside a same package. Chips or packages may be stacked vertically, side-by-side horizontally, or tiled horizontally on a substrate and interconnected by wire bonds or solder bumps. The approach typically has been used for applications where performance and low power are critical. Communication between chips is accomplished using either a silicon or organic interposer, typically a chip or layer with through-silicon vias for inter-chip communication. While communication between chips is slower than on-chip communication, distances are shorter and there are more conduits for signals. Collectively, communication is faster, and less energy is required to drive those signals. In addition, distances can be shorter between chips than within a single planar die, and at advanced nodes, skinny wires in single-chip architectures can slow performance and increase resistance and capacitance.
FIG. 2 illustrates a prior art cut-away view of a 2.5D/3DIC SiP (Silicon Package) 20 mounted on a printed circuit board. The silicon package 20 is mounted on a portion of a printed circuit board 210. Package bumps 212, SiP substrate 214, and flip-chip bumps 216 provide an interface to a silicon interposer 218 that includes topside metal layers, interposer substrate, backside metal layers, and through-silicon vias (TSVs). The micro-bumps 220 provide an interface to Die #1 and Die #2.
FIG. 3 illustrates a prior art cut-away view of a 2.5D package 30 having a silicon interposer 330 with stacks of varying heights. The 2.5D package 30 is mounted on a portion of a printed circuit board 310. A SiP substrate 320 and silicon interposer 330 provide interfaces to Die #1, Die #2, Die #3, Die #4, Die #5, and Die #6 using package bumps, flip-chip bumps, micro-bumps, and though-silicon vias (TSVs) as discussed above and with respect to FIG. 2.
As shown in FIG. 3 and due to different various functions of the dice, there will be different die thicknesses affecting the height of the 2.5D package. Currently, most applications of heatsink interfaces use thermal interface materials (TIMs) that make a contact onto a single contact surface. There are an increasing number of applications where a single TIM layer is expected to conform to the varying die heights from variances in flatness caused by reflow or package tilt acceptable by JEDEC standards. However, deviations from the standards have adverse consequences for TIMs. TIMs and many other interfacing materials are rigid and do not perform optimally if non-flat. Even for heatsinks interfacing with multiple packages of a same specified height, variations in manufacturing and assembly can result in relatively uneven surfaces from a TIM perspective. Given the variations and manufacturing tolerances on heights between die packages, non-bonded TIMs interfacing with heatsinks may be the best option. The non-bonded TIMs can accommodate variations in package heights as long as minimal pressure can be maintained for good contact resistance. Moreover, mechanical stress interaction between the packages from thermal cycling can be minimized using non-bonded TIMs.
Similarly, 3DIC SiP (System-in-Package) typically feature power dissipating components at the bottom of the stack. Memory components which are placed higher and can be subjected to thermal cross talk from heat dissipation of the bottom components. Depending on the package heights of a complex 2.5D/3DIC SiP. TIMs heights ranging from 50 um to 1 mm or more may be needed to efficiently interface heatsinks to the chip packages. Moreover, the foregoing challenges are further magnified in photonic packaging applications. Temperature fluctuations in photonic packaging can cause adverse wavelength shifts that have forced design engineers to look for innovative thermal management solutions.
Accordingly, there is a need to provide a thermal interface that overcomes the short comings of current thermal management techniques. A novel thermal management system, method, and apparatus of using unique TIMs to address heat dissipation of system component are provided.